View STA8088EXG_8295681.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

for further information contact your local stmicroelectronics sales office. september 2014 docid022725 rev 6 1/24 STA8088EXG flexible gps/galileo/glonass/qzss receiver with high performance processing (arm9) data brief features ? stmicroelectronics ? 3rd generation positioning receiver with 32 tracking channels and 2 fast acquisition channels compatible with gps, galileo, glonass and qzss systems ? embedded rf front-end with built-in lna ? -162dbm indoor sensitivity (tracking mode) ? fast ttff < 1 s in hot start and 35 s in cold start ? support of st-agpstm multimode assisted gps (extended ephemeris solution) ? high performance arm946 mcu (up to 208 mhz) ? 256 kbyte embedded tcm/sram ? fsmc external memory interface (nand, nor and sram) ? external sqi flash interface ? one 16-bit extended function timer (eft) with input capture/ output compare and pwm. ? four 32-bit free running timers/ counters ? real time clock (rtc) circuit ? 3 uarts (one full for modem support) ? 1 i 2 c master/slave interface ? 1 synchronous serial port (ssp, motorola-spi supported) ? usb2.0 dual role full speed (12 mhz) with integrated physical layer transceiver ? 2 secure-digital multimedia memory card interfaces (sdmmc) ? 2 controller area network (can) ? 1 multichannel serial port (msp) ? gpio port for a total of up to 64 gpios ? 8-channels adc (10 bit) ? selectable 1.8 v or 3.3 v i/os for specific i/o ports ? 3 embedded 1.8 v voltage regultators ? operating condition: ?v dd12 : 1.2 v 10 % ?v dd18/rf18 : 1.8 v 5 % ?v lpvr : 1.62 v to 3.6 v ?v ddio : 1.8 v -5 %/ +10 %; 3.3 v 10 % ? package: ? tfbga169 9 x 9 x 1.2 mm 0.65 pitch ? tfbga169 12 x 12 x 1.2 mm 0.8 pitch ? ambient temperature range: -40/ +85 c description STA8088EXG is a single die standalone positioning receiver ic working on multiple constellations (gps/galileo/glonass/qzss). by combining the arm946 microcontroller core with the large number of peripherals/ interfaces, STA8088EXG provides a highly-flexible and cost effective solution for hand-held and telematic applications. the device is the ideal solution for sensor-based and sensor-less st dead reckoning technologies which enhance positioning accuracy even in areas without gnss signals, like tunnels and indoor parking. tfbga169 www.st.com
contents STA8088EXG 2/24 docid022725 rev 6 contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 tfbga169 ball out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 power supply pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.4 main function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.5 test / emulated dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.6 fsmc external memory interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.7 sqi pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.8 port 0 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.9 port 1 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.10 rf front-end pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3 package and packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.1 ecopack ? packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 tfbga169 9 x 9 x 1.2 mm package information . . . . . . . . . . . . . . . . . . . 18 3.3 tfbga169 12 x 12 x 1.2 mm package information . . . . . . . . . . . . . . . . . 20 4 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
docid022725 rev 6 3/24 STA8088EXG list of tables 3 list of tables table 1. tfbga169 ball out automotive grade (with can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. tfbga169 ball out (no can) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. power supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. main function pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 5. test/emulated dedicated pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. fsmc memory interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. sqi pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 8. port 0 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 9. port 1 pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 10. rf front-end pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 table 11. tfbga169 9 x 9 x 1.2 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 12. tfbga169 12 x 12 x 1.2 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 13. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
list of figures STA8088EXG 4/24 docid022725 rev 6 list of figures figure 1. STA8088EXG system block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. tfbga169 9 x 9 x 1.2 mm package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 3. tfbga169 12 x 12 x 1.2 mm package dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 4. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
docid022725 rev 6 5/24 STA8088EXG overview 23 1 overview STA8088EXG is an integrated system-on-chip device designed for a highly-flexible and cost effective solution for vehicle, hand-held navigation and telematic applications. it combines a high performance arm946 microprocessor with embedded enhanced peripherals and i/o capabilities, rf front-end and base band processor to support gps, galileo, glonass and qzss satellite systems. it also provides clock generation via pll, backup logic with real time clock and it supports usb2.0 standard at full speed. STA8088EXG is software compatible with the arm processor family. the device is power supplied with 1.8 v and uses three on-chip voltage regulators to internally supply the rf front-end, core logic the backup logic. in order to reduce the power consumption the chip can be directly powered with 1.2 v bypassing the embedded voltage regulators. i/o lines are compatible with 1.8 v and 3.3 v. the chip, using stmicroelectronics cmosrf technology, is housed in a tfbga169 (9 x 9 x 1.2 mm) and tfbga169 (12 x 12 x 1.2 mm) packages. the automotive grade devices (see figure 4: ordering information scheme ) fulfilling high quality and service level automotive market requirements, is the ideal solution for oem telematic applications.
pin description STA8088EXG 6/24 docid022725 rev 6 2 pin description 2.1 block diagram figure 1. STA8088EXG system block diagram %.bgrpdlq 64, ,) )60& ,) 86% ,) 9,& 520 .% $+% '&5(* 26&, 7+6(16 6$5$'& $'6$0b 26&, 26&,b/-b9 3:5567 &/. &75/ ,62 &(// ,& 663 8$57 5[ 7[ 5(*0$3 $3% %ulgjh 063 8$57 5[ 7[ 8$57 )xoo &$1 &$1 $'& 078 *3,2 6'00& ()7 :' $3% $50 ,&dfkh .% '&dfkh .% +,*+63((', 7&0 .% .+,*+63((''7&0 ,'6:,7&+$%/(7&0 [.% $3% %ulgjh 6<6&75/ 57& $3% 5$0.% *%dvh%dqg *orqdvv,) *$/*36,) )dvw$ft &kdqqho 7un &kdqqhov 0x[ $ft 5$0v $3% %ulgjh '&b/1b9729 +35(* /35(* %.5(* &/2&.b*(1 &.; 3// 3*b[ )5&b'3// 5,26& 7hvwfrqwuroohu ,2v 67$(; -7$* *5),3 9 ? 9 '&5(* 63,,) 26&, 0+] 5) 6hfwlrq /1$ 6hfwlrq $'& *$/*36 $'& */21$66
STA8088EXG pin description docid022725 rev 6 7/24 2.2 tfbga169 ball out table 1. tfbga169 ball out automotive grade (with can) 12 3 4 5678910111213 a gndio usb_dm (uart1_rx) usb_dp (uart1_tx) can0tx fsmc add22 (p1.30) fsmc add18 (p1.26) fsmc add9 (p1.17) fsmc add16 (p1.24) fsmc data15 fsmc data8 fsmc data5 fsmc data4 gndio b vddio_r2 can1tx (p0.8) can1rx (p0.9) can0rx fsmc add23 (p1.31) fsmc add19 (p1.27) fsmc add6 (p1.14) fsmc add10 (p1.18) fsmc data14 fsmc data2 vddio_r3 fsmc bln1 fsmc bln0 c mspout sclk (p0.31) mspout lrclk (p0.30) mspout_sd/ iopwrsel_r2 (p0.29) vddio_r5 fsmc wtn fsmc add20 (p1.28) fsmc add1 (p1.9) fsmc add14 (p1.22) fsmc data12 fsmc data10 fsmc cs2 fsmc_cs3/ iopwrsel_r3 fsmc data0 d mmc_clk mmc_cmd (p0.28) vdd18 mvr vdd12_mvr fsmc wen fsmc add21 (p1.29) fsmc add2 (p1.10) fsmc add11 (p1.19) fsmc clk fsmc adv fsmc data9 fsmc cs1 fsmc cs0 e mmc_d0 (p0.20) mmc_d1 (p0.21) mmc_d2 (p0.22) mmc_d3 (p0.23) fsmc outen fsmc add4 (p1.12) fsmc add7 (p1.15) fsmc add17 (p1.25) fsmc add13 (p1.21) fsmc data1 fsmc data3 gpio2 (p0.2) gpio5 (p0.5) f mmc_d4 (p0.24) mmc_d5 (p0.25) mmc_d6 (p0.26) mmc_d7 (p0.27) fsmc add5 (p1.13) fsmc add3 (p1.11) fsmc add0 (p1.8) fsmc add8 (p1.16) fsmc add12 (p1.20) fsmc data7 spi_clk (p1.1) gpio1 (p0.1) gpio4 (p0.4) g tms trstn tdi tck gnd gnd gnd vdd18 mvr fsmc data11 fsmc data6 spi_do (p1.3) vddio_r1 gpio7 (p0.7) h vrf12 rfadc tp_if_p gnd_rf tdo vdd12 lpvr gndio gnd gnd fsmc add15 (p1.23) fsmc data13 spi_di (p1.2) gpio3 (p0.3) gpio6 (p0.6) j vrf12 lna tp_if_n gnd_rf gnd_rf stby_out stdbyn vdd12_mvr vdd lpvr vdd12_mvr pps_out spi_csn/ iopwrsel_r1 (p1.0) uart0 rts (p0.14) gpio0 (p0.0) k lna in gnd lna gnd_rf gnd_rf gnd_rf gnd_rf wakeup rstn adc_in8 vddio_r4 uart2_tx/ boot_0 (p1.5) uart2_rx (p1.4) uart0_tx/ boot_1 (p1.7) l gnd lna gnd lna gnd_rf gnd_rf vrf12 rfvco vrf12 rfdig adc_in1 adc_in4 adc_in2 sqi_sio2 (p0.12) sqi_sck uart0 dtr (p0.18) uart0_rx (p1.6) m lna out vrf18 rfvr gnd_rf gnd_rf vrf12 mix xtal out adc_in3 adc_in6 rtc_xti sqi_sio1 (p0.11) sqi_cen/ iopwrsel_r4 (p0.19) uart0 cts (p0.15) uart0 dsr (p0.16) n gnd_rf vrf12out rfvr vrf12 rfa rfa in vrf12_if xtal in adc_in7 adc_in5 rtc_xto sqi_sio3 (p0.13) sqi_sio0 (p0.10) uart0 dcd (p0.17) gndio
pin description STA8088EXG 8/24 docid022725 rev 6 table 2. tfbga169 ball out (no can) 1 2 3 4 5 6 7 8 9 10 11 12 13 a gndio usb_dm (uart1_rx) usb_dp (uart1_tx) n.c. fsmc add22 (p1.30) fsmc add18 (p1.26) fsmc add9 (p1.17) fsmc add16 (p1.24) fsmc data15 fsmc data8 fsmc data5 fsmc data4 gndio b vddio_r2 i2c_sd (p0.8) i2c_sclk (p0.9) n.c. fsmc add23 (p1.31) fsmc add19 (p1.27) fsmc add6 (p1.14) fsmc add10 (p1.18) fsmc data14 fsmc data2 vddio_r3 fsmc bln1 fsmc bln0 c mspout sclk (p0.31) mspout lrclk (p0.30) mspout_sd/ iopwrsel_r2 (p0.29) vddio_r5 fsmc wtn fsmc add20 (p1.28) fsmc add1 (p1.9) fsmc add14 (p1.22) fsmc data12 fsmc data10 fsmc cs2 fsmc_cs3/ iopwrsel_r3 fsmc data0 d mmc_clk mmc_cmd (p0.28) vdd18 mvr vdd12_mvr fsmc wen fsmc add21 (p1.29) fsmc add2 (p1.10) fsmc add11 (p1.19) fsmc clk fsmc adv fsmc data9 fsmc cs1 fsmc cs0 e mmc_d0 (p0.20) mmc_d1 (p0.21) mmc_d2 (p0.22) mmc_d3 (p0.23) fsmc outen fsmc add4 (p1.12) fsmc add7 (p1.15) fsmc add17 (p1.25) fsmc add13 (p1.21) fsmc data1 fsmc data3 gpio2 (p0.2) gpio5 (p0.5) f mmc_d4 (p0.24) mmc_d5 (p0.25) mmc_d6 (p0.26) mmc_d7 (p0.27) fsmc add5 (p1.13) fsmc add3 (p1.11) fsmc add0 (p1.8) fsmc add8 (p1.16) fsmc add12 (p1.20) fsmc data7 spi_clk (p1.1) gpio1 (p0.1) gpio4 (p0.4) g tms trstn tdi tck gnd gnd gnd vdd18 mvr fsmc data11 fsmc data6 spi_do (p1.3) vddio_r1 gpio7 (p0.7) h vrf12 rfadc tp_if_p gnd_rf tdo vdd12 lpvr gndio gnd gnd fsmc add15 (p1.23) fsmc data13 spi_di (p1.2) gpio3 (p0.3) gpio6 (p0.6) j vrf12 lna tp_if_n gnd_rf gnd_rf stby_out stdbyn vdd12_mvr vdd lpvr vdd12_mvr pps_out spi_csn/ iopwrsel_r1 (p1.0) uart0 rts (p0.14) gpio0 (p0.0) k lna in gnd lna gnd_rf gnd_rf gnd_rf gnd_rf wakeup rstn adc_in8 vddio_r4 uart2_tx/ boot_0 (p1.5) uart2_rx (p1.4) uart0_tx/ boot_1 (p1.7) l gnd lna gnd lna gnd_rf gnd_rf vrf12 rfvco vrf12 rfdig adc_in1 adc_in4 adc_in2 sqi_sio2 (p0.12) sqi_sck uart0 dtr (p0.18) uart0_rx (p1.6) m lna out vrf18 rfvr gnd_rf gnd_rf vrf12 mix xtal out adc_in3 adc_in6 rtc_xti sqi_sio1 (p0.11) sqi_cen/ iopwrsel_r4 (p0.19) uart0 cts (p0.15) uart0 dsr (p0.16) n gnd_rf vrf12out rfvr vrf12 rfa rfa in vrf12_if xtal in adc_in7 adc_in5 rtc_xto sqi_sio3 (p0.13) sqi_sio0 (p0.10) uart0 dcd (p0.17) gndio
docid022725 rev 6 9/24 STA8088EXG pin description 23 2.3 power supply pins table 3. power supply pins symbol i/o functions tfbga169 vdd18_mvr pwr digital supply voltage for main voltage regulator (1.8 v) d3, g8 vdd12_mvr pwr digital supply voltage for core circuitry (1.2 v). when using the mvr, this pin shall not be driven by an external voltage supply, but a capacitance shall be connected between these pins and gnd to guarantee on-chip voltage stability. j7, d4, j9 vdd_lpvr pwr digital supply voltage for low power voltage regulator (1.62 v - 3.6 v) j8 vdd12_lpvr pwr digital supply voltage for backup logic (1.2 v). when using the lpvr, this pin shall not be driven by an external voltage supply, but a capacitance shall be connected between these pins and gnd to guarantee on-chip voltage stability. h5 vdd_ior1 pwr digital supply voltage for i/o ring 1 (1.8 v or 3.3 v) g12 vdd_ior2 pwr digital supply voltage for i/o ring 2 (1.8 v or 3.3 v) b1 vdd_ior3 pwr digital supply voltage for i/o ring 3 (1.8 v or 3.3 v) b11 vdd_ior4 pwr digital supply voltage for i/o ring 4 (1.8 v or 3.3 v) k10 vdd_ior5 pwr digital supply voltage for i/o ring 5 (3.3 v) c4 vrf18_rfvr pwr analog supply voltage for rf voltage regulator (1.8 v) m2 gnd gnd digital supply ground for core (5 pins) g5, g6, g7, h7, h8 gnd_io gnd digital supply ground for i/o circuitry (4 pins) a1, a13, h6, n13 vrf12out_rfvr pwr rf voltage regulator 1.2 v output n2 vrf12_lna pwr analog supply voltage for lna (1.2 v) j1 vrf12_rfa pwr analog supply voltage for rfa (1.2 v) n3 vrf12_mix pwr analog supply voltage for mixer (1.2 v) m5 vrf12_if pwr analog supply voltage for if (1.2 v) n5 vrf12_rfdig pwr analog supply voltage for rf digital (1.2 v) l6 vrf12_rfvco pwr analog supply voltage for vco (1.2 v) l5 vrf12_rfadc pwr analog supply voltage for rf adc (1.2 v) h1 gnd_lna gnd analog supply ground for lna (3 pins) k2, l1, l2 gnd_rf gnd analog supply ground to rf (12 pins) h3, j3, j4, k3, k4, k5, k6, l3, l4, m3, m4, n1
pin description STA8088EXG 10/24 docid022725 rev 6 2.4 main function pins 2.5 test / emulated dedicated pins table 4. main function pins symbol i/o voltage i/o functions tfbga169 rstn (1) 1.2 v i reset input with schmitt-trigger characteristics and noise filter. k8 stdbyn 1.2 v i when low, the chip is forced in standby mode. all pins in high impedance except the ones powered by backup supply j6 wakeup (2) 1.2 v i wakeup from standby mode k7 stdby_out 1.2 v o when low, indicates the chip is in standby mode. j5 pps_out vdd_ior1 o pulsed per second output j10 rtc_xti 1.5 v (max) i input of the 32 khz oscillator amplifier circuit and input of the internal real time clock circuit. m9 rtc_xto 1.5 v (max) o output of the oscillator amplifier circuit. n9 can0tx (3) vdd_ior5 o can 0 - transmit data output a4 can0rx (3) vdd_ior5 i can 0 - receive data input b4 usb_dm/uart1_rx vdd_ior5 usb/i usb d- signal / uart 1 rx data a2 usb_dp/uart1_tx vdd_ior5 usb/o usb d+ signal / uart 1 tx data a3 adc_in[1:8] 1.4 v ? 0 v typ range i adc analog input [1:8] l7, l9, m7, l8, n8, m8, n7, k9 mmc_clk vdd_ior2 o mmc_clk: multimedia clock line d1 1. when rstn is de-asserted, pin wakeup must be low. 2. the wakeup pulse must be longer than 500 s. 3. only for automotive grade devices. table 5. test/emulated dedicated pins symbol i/o voltage i/o functions tfbga169 tck vdd_ior5 i jtag test clock g4 tdi vdd_ior5 i jtag test data in g3 tdo vdd_ior5 o jtag test data out h4 tms vdd_ior5 i jtag test mode select g1 trstn (1) vdd_ior5 i jtag test circuit reset g2 tp_if_p vrf12_if o diff. test point for if ? positive h2 tp_if_n vrf12_if o diff. test point for if ? negative j2 1. if jtag interface is not used, pin trstn must be asserted low.
docid022725 rev 6 11/24 STA8088EXG pin description 23 2.6 fsmc external memory interface pins 2.7 sqi pins table 6. fsmc memory interface pins symbol i/o voltage i/o functions tfbga169 fsmc_data[15:0] vdd_ior3 i/o fsmc emi data bus c13, e10, b10, e11, a12, a11, g10, f10, a10, d11, c10, g9, c9, h10, b9, a9 fsmc_add[23:0] (1)(2) vdd_ior3 o fsmc emi address bus f7, c7, d7, f6, e6, f5, b7, e7, f8, a7, b8, d8, f9, e9, c8, h9, a8, e8, a6, b6, c6, d6, a5, b5 fsmc _outen vdd_ior3 o fsmc emi output enable e5 fsmc _wen vdd_ior3 o fsmc emi write enable d5 fsmc _wtn vdd_ior3 i fsmc emi wait (snor, cram) c5 fsmc _bln[0,1] vdd_ior3 o fsmc emi byte lane b13, b12 fsmc _clk vdd_ior3 o fsmc emi clk d9 fsmc _adv vdd_ior3 o fsmc emi address valid d10 fsmc _cs0 vdd_ior3 o fsmc emi chip select for external memory bank 0 d13 fsmc _cs1 vdd_ior3 o fsmc emi chip select for external memory bank 1 d12 fsmc _cs2 vdd_ior3 o fsmc emi chip select for external memory bank 2 c11 fsmc _cs3/ iopwrsel_r3 vdd_ior3 o fsmc emi chip select for external memory bank 3 / i/o ring 3 power selection c12 1. fsmc_add[23:0] are multiplexed with p1[31:8] - see table 9 2. in case of nand memory usage the fsmc_add16 is used as cle fsmc_add17 is used as ale table 7. sqi pins symbol i/o voltage i/o functions tfbga169 sqi_sio3 vdd_ior4 i/o sqi flash data i/o 3 n10 sqi_sio2 vdd_ior4 i/o sqi flash data i/o 2 l10 sqi_sio1/so vdd_ior4 i/o sqi flash data i/o 1 / ser. o m10 sqi_sio0/si vdd_ior4 i/o sqi flash data i/o 0 / ser. i n11
pin description STA8088EXG 12/24 docid022725 rev 6 sqi pins are multiplexed with p0[13:10] and p0[19] (see table 8 ). 2.8 port 0 pins port 0 consists of a 32-bit bidirectional i/o port. it can be either used as general purpose input or output port, or configured according to the associated alternate functions. sqi_sck vdd_ior4 o sqi flash clock l11 sqi_cen/ iopwrsel_r4 vdd_ior4 o sqi flash chip enable / i/o ring 4 power selection m11 table 7. sqi pins (continued) symbol i/o voltage i/o functions tfbga169 table 8. port 0 pins symbol i/o voltage i/o mode functions tfbga169 p0.0 vdd_ior1 i/o default gpio.0: general purpose i/o j13 i a pps_in: pulse per second input o b pps_out: pulse per second output o c sqi_cen: sqi flash chip enable p0.1 vdd_ior1 i/o default gpio.1: general purpose i/o f12 o a rtc_clko: rtc clock out p0.2 vdd_ior1 i/o default gpio.2: general purpose i/o e12 o a mmc2_clk: mmc 2 clock line p0.3 vdd_ior1 i/o default gpio.3: general purpose i/o h12 i/o a mmc2_cmd: mmc 2 command line p0.4 vdd_ior1 i/o default gpio.4: general purpose i/o f13 i/o a mmc2_data3: mmc 2 data 3 p0.5 vdd_ior1 i/o default gpio.5: general purpose i/o e13 i/o a mmc2_data2: mmc 2 data 2 p0.6 vdd_ior1 i/o default gpio.6: general purpose i/o h13 i/o a mmc2_data1: mmc 2 data 1 p0.7 vdd_ior1 i/o default gpio.7: general purpose i/o g13 i/o a mmc2_data0: mmc 2 data 0 p0.8 vdd_ior5 o default can1tx (1) : can 1 transmit data output b2 i/o a gpio.8: general purpose i/o i/o b i2c_sd: i2c serial data
docid022725 rev 6 13/24 STA8088EXG pin description 23 p0.9 vdd_ior5 i default can1rx (1) : can 1 receive data input b3 i/o a gpio.9: general purpose i/o o b i2c_sclk: i2c clock p0.10 vdd_ior4 i/o default sqi_sio0/si: sqi flash data i/o 0 / ser. i n11 i/o a gpio10: general purpose i/o p0.11 vdd_ior4 i/o default sqi_sio1/so: sqi flash data i/o 1 / ser. o m10 i/o a gpio11: general purpose i/o p0.12 vdd_ior4 i/o default sqi_sio2: sqi flash data i/o 2 l10 i/o a gpio12: general purpose i/o p0.13 vdd_ior4 i/o default sqi_sio3: sqi flash data i/o 3 n10 i/o a gpio13: general purpose i/o p0.14 vdd_ior1 o default uart0_rts: uart0 request to send j12 i/o a gpio14: general purpose i/o i c mspin_sclk: msp serial clock input p0.15 vdd_ior1 i default uart0_cts: uart0 clear to send m12 i/o a gpio15: general purpose i/o ib timer_icapa: extended function timer - input capture a i c mspin_lrclk: msp left/right clock input p0.16 vdd_ior1 i default uart0_dsr: uart0 data set ready m13 i/o a gpio16: general purpose i/o ob timer_ocmpa: extended function timer ? output compare a i c mspin_sd: msp serial data input p0.17 vdd_ior1 i default uart0_dcd: uart0 data carrier detect n12 i/o a gpio17: general purpose i/o ib timer_icapb: extended function timer - input capture b p0.18 vdd_ior1 o default uart0_dtr: uart0 data terminal read l12 i/o a gpio18: general purpose i/o ob timer_ocmpb: extended function timer ? output compare b p0.19 vdd_ior4 odefault sqi_cen/iopwrsel_r4: sqi flash chip enable / i/o ring 4 power selection m11 i/o a gpio19: general purpose i/o table 8. port 0 pins (continued) symbol i/o voltage i/o mode functions tfbga169
pin description STA8088EXG 14/24 docid022725 rev 6 p0.20 vdd_ior2 i/o default mmc_data0: multimedia card data 0 e1 i/o a gpio20: general purpose i/o o b mag_0gns: gns 3bit coding output (mag0) p0.21 vdd_ior2 i/o default mmc_data1: multimedia card data 1 e2 i/o a gpio21: general purpose i/o o b mag_1gns: gns 3bit coding output (mag1) p0.22 vdd_ior2 i/o default mmc_data2: multimedia card data 2 e3 i/o a gpio22: general purpose i/o i/o b mag_0ggps: ggps 3bit coding output (mag0) p0.23 vdd_ior2 i/o default mmc_data3: multimedia card data 3 e4 i/o a gpio23: general purpose i/o i/o b mag_1ggps: ggps 3bit coding output (mag1) p0.24 vdd_ior2 i/o default mmc_data4: multimedia card data 4 f1 i/o a gpio24: general purpose i/o p0.25 vdd_ior2 i/o default mmc_data5: multimedia card data 5 f2 i/o a gpio25: general purpose i/o p0.26 vdd_ior2 i/o default mmc_data6: multimedia card data 6 f3 i/o a gpio26: general purpose i/o p0.27 vdd_ior2 i/o default mmc_data7: multimedia card data 7 f4 i/o a gpio27: general purpose i/o p0.28 vdd_ior2 i/o default mmc_cmd: multimedia card command line d2 i/o a gpio28: general purpose i/o p0.29 vdd_ior2 odefault mspout_sdata/iopwrsel_r2: msp serial data output/ i/o ring 2 power selection c3 i/o a gpio29: general purpose i/o p0.30 vdd_ior2 o default mspout_lrclk msp left/right clock output c2 i/o a gpio30: general purpose i/o p0.31 vdd_ior2 o default mspout_sclk: msp serial clock output c1 i/o a gpio31: general purpose i/o o b prnseq0 1. only for automotive grade devices. table 8. port 0 pins (continued) symbol i/o voltage i/o mode functions tfbga169
docid022725 rev 6 15/24 STA8088EXG pin description 23 2.9 port 1 pins port 1 consists of a 32-bit bidirectional i/o port. it can be either used as general purpose input or output port, or configured according to the associated alternate functions. table 9. port 1 pins symbol i/o voltage i/o mode functions tfbga169 p1.0 vdd_ior1 odefault ssp_csn/iopwrsel_r1: ssp chip select active low / i/o ring 1 power selection j11 i/o a gpio32: general purpose i/o i/o b signggps: ggps 3bit coding output (sign) o c sqi_cen: sqi flash chip enable p1.1 vdd_ior1 i/o default ssp_clk: ssp clock f11 i/o a gpio33: general purpose i/o i/o b clock_ggps: ggps clock out o c sqi_clk: sqi flash clock p1.2 vdd_ior1 i default ssp_di: ssp serial data input h11 i/o a gpio34: general purpose i/o i/o b signgns: gns 3bit coding output (sign) i/o c sqi_sio0/si: sqi flash data i/o 0 / ser. i p1.3 vdd_ior1 o default ssp_do: ssp serial data output g11 i/o a gpio35: general purpose i/o i/o b clock_gns: gns clock out i/o c sqi_sio1/so: sqi flash data i/o 1 / ser. o p1.4 vdd_ior1 i default uart2_rx: uart 2 rx data k12 i/o a gpio36: general purpose i/o p1.5 vdd_ior1 o default uart2_tx: uart 2 tx data / arm boot 0 k11 i/o a gpio37: general purpose i/o p1.6 vdd_ior1 i default uart0_rx: uart 0 rx data l13 i/o a gpio38: general purpose i/o i/o c sqi_sio2: sqi flash data i/o 2 p1.7 vdd_ior1 o default uart0_tx: uart 0 tx data / arm boot 1 k13 i/o a gpio39: general purpose i/o i/o c sqi_sio3: sqi flash data i/o 3 p1.8 vdd_ior3 o default fsmc_add0: fsmc emi address bus 0 f7 i/o a gpio40: general purpose i/o
pin description STA8088EXG 16/24 docid022725 rev 6 p1.9 vdd_ior3 o default fsmc_add1: fsmc emi address bus 1 c7 i/o a gpio41: general purpose i/o p1.10 vdd_ior3 o default fsmc_add2: fsmc emi address bus 2 d7 i/o a gpio42: general purpose i/o p1.11 vdd_ior3 o default fsmc_add3: fsmc emi address bus 3 f6 i/o a gpio43: general purpose i/o p1.12 vdd_ior3 o default fsmc_add4: fsmc emi address bus 4 e6 i/o a gpio44: general purpose i/o p1.13 vdd_ior3 o default fsmc_add5: fsmc emi address bus 5 f5 i/o a gpio45: general purpose i/o p1.14 vdd_ior3 o default fsmc_add6: fsmc emi address bus 6 b7 i/o a gpio46: general purpose i/o p1.15 vdd_ior3 o default fsmc_add7: fsmc emi address bus 7 e7 i/o a gpio47: general purpose i/o p1.16 vdd_ior3 o default fsmc_add8: fsmc emi address bus 8 f8 i/o a gpio48: general purpose i/o p1.17 vdd_ior3 o default fsmc_add9: fsmc emi address bus 9 a7 i/o a gpio49: general purpose i/o p1.18 vdd_ior3 o default fsmc_add10: fsmc emi address bus 10 b8 i/o a gpio50: general purpose i/o p1.19 vdd_ior3 o default fsmc_add11: fsmc emi address bus 11 d8 i/o a gpio51: general purpose i/o p1.20 vdd_ior3 o default fsmc_add12: fsmc emi address bus 12 f9 i/o a gpio52: general purpose i/o p1.21 vdd_ior3 o default fsmc_add13: fsmc emi address bus 13 e9 i/o a gpio53: general purpose i/o p1.22 vdd_ior3 o default fsmc_add14: fsmc emi address bus 14 c8 i/o a gpio54: general purpose i/o p1.23 vdd_ior3 o default fsmc_add15: fsmc emi address bus 15 h9 oatcxo_clk p1.24 vdd_ior3 odefault fsmc_add16/cle: fsmc emi address bus 16/cle a8 i/o a gpio56: general purpose i/o table 9. port 1 pins (continued) symbol i/o voltage i/o mode functions tfbga169
docid022725 rev 6 17/24 STA8088EXG pin description 23 2.10 rf front-end pins p1.25 vdd_ior3 odefault fsmc_add17/ale: fsmc emi address bus 17/ale e8 i/o a gpio57: general purpose i/o p1.26 vdd_ior3 o default fsmc_add18: fsmc emi address bus 18 a6 i/o a gpio58: general purpose i/o p1.27 vdd_ior3 o default fsmc_add19: fsmc emi address bus19 b6 i/o a gpio59: general purpose i/o p1.28 vdd_ior3 o default fsmc_add20: fsmc emi address bus 20 c6 i/o a gpio60: general purpose i/o p1.29 vdd_ior3 o default fsmc_add21: fsmc emi address bus 21 d6 i/o a gpio61: general purpose i/o p1.30 vdd_ior3 o default fsmc_add22: fsmc emi address bus 22 a5 i/o a gpio62: general purpose i/o p1.31 vdd_ior3 o default fsmc_add23: fsmc emi address bus 23 b5 i/o a gpio63: general purpose i/o table 9. port 1 pins (continued) symbol i/o voltage i/o mode functions tfbga169 table 10. rf front-end pins symbol i/o voltage i/o functions tfbga169 lna_in vrf12_lna i low noise amplifier input k1 lna_out vrf12_lna o low noise amplifier output m1 rfa_in vrf12_rfa i rf amplifier input n4 xtal_in vrf12_rfdig i input side of crystal oscillator or tcxo input n6 xtal_out vrf12_rfdig o output side of crystal oscillator m6
package and packing information STA8088EXG 18/24 docid022725 rev 6 3 package and packing information 3.1 ecopack ? packages in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 3.2 tfbga169 9 x 9 x 1.2 mm package information table 11. tfbga169 9 x 9 x 1.2 mm mechanical data ref. dim data book (mm) drawing (mm) min. typ. max. min. typ. max. a (1) 1. tfbga stands for thin profile fine pitch ball grid array. - the total profile height (dim a) is measured from the seating plane to the top of the component - the maximum total package height is calculated by the following methodology: a max = a1 typ + a2 typ + a4 typ + (a1 2 + a2 2 + a4 2 tolerance values) - thin profile: 1.00 mm < a 1.20 mm / fine pitch: e < 1.00 mm pitch. 1.20 1.07 a1 (2) 2. - the terminal a1 corner must be identified on the t op surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. - a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. exact shape of each corner is optional. 0.21 0.22 0.27 0.32 a2 0.20 0.16 0.20 0.24 a4 0.585 0.57 0.585 0.60 b (3) 3. the typical ball diameter before mounting is 0.35 mm. 0.30 0.35 0.40 0.30 0.35 0.40 d 8.85 9.00 9.15 8.90 9.00 9.10 d1 7.80 7.80 e 9.85 9.00 9.15 8.90 9.00 9.10 e1 7.80 7.80 e 0.65 0.65 z 0.60 0.60 ddd 0.08 0.08 eee (4) 4. the tolerance of position that controls the location of the pattern of balls with respect to datums a and b. for each ball there is a cylindric al tolerance zone eee perpendicular to datum c and located on true position with respect to datums a and b as defined by e. the axis perpendicular to datum c of each ball must lie within this tolerance zone. 0.15 0.15 fff (5) 0.05 0.05
docid022725 rev 6 19/24 STA8088EXG package and packing information 23 figure 2. tfbga169 9 x 9 x 1.2 mm package dimension 1. - the terminal a1 corner must be identified on the t op surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heatslug. - a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. exact shape of eac h corner is optional. 5. the tolerance of position that controls the location of the balls within the matrix with respect to each other.for each ball there is a cyli ndrical tolerance zone fff perpendicular to datum c and located on true position as defined by e. the axis per pendicular to datum c of each ball must lie within this tolerance zone. each tolerance zone fff in the array is contained entirely in the respecti ve zone eee above. the axis of each ball must lie simultaneously in both tolerance zones.
package and packing information STA8088EXG 20/24 docid022725 rev 6 3.3 tfbga169 12 x 12 x 1.2 mm package information table 12. tfbga169 12 x 12 x 1.2 mm mechanical data ref. dim data book (mm) drawing (mm) min. typ. max. min. typ. max. a (1) 1. tfbga stands for thin profile fine pitch ball grid array. ? thin profile: 1.00mm < a . 1.20mm / fine pitch: e < 1.00mm. ? the total profile height (dim a) is measured from the seating plane gch to the top of the component. ? the maximum total package height is calculated by the rss method (root sum square): a max = a1 typ + a2 typ + a4 typ + ? (a12 + a22 + a42 tolerance values). 1.20 1.15 a1 (2) 2. ? the terminal a1 corner must be identified on the top surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heat slug. ? a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. exact shape of each corner is optional. 0.21 0.25 0.30 0.35 a2 0.20 0.16 0.20 0.24 a4 0.60 0.57 0.585 0.60 b (3) 3. the typical ball diameter before mounting is 0.40 mm. 0.35 0.40 0.45 0.35 0.40 0.45 d 11.85 12.00 11.85 11.90 12.00 12.10 d1 9.60 9.60 e 11.85 12.00 11.85 11.90 12.00 12.10 e1 9.60 9.60 e 0.80 0.80 z 1.20 1.20 ddd 0.10 0.10 eee (4) 4. the tolerance of position that controls the location of the pattern of balls with respect to datums a and b. for each ball there is a cylindric al tolerance zone eee perpendicular to datum c and located on true position with respect to datums a and b as defined by e. the axis perpendicular to datum c of each ball must lie within this tolerance zone. 0.15 0.15 fff (5) 5. the tolerance of position that controls the location of the balls within the matrix with respect to each other. for each ball there is a cylindrical tolerance zone fff perpendicular to datum c and located on true position as defined by e. the axis perpendicular to datum c of each ball must lie within this tolerance zone. each tolerance zone fff in the array is contained entirely in the respective zone eee above the axis of each ball must lie simultaneously in both tolerance zones. 0.08 0.08
docid022725 rev 6 21/24 STA8088EXG package and packing information 23 figure 3. tfbga169 12 x 12 x 1.2 mm package dimension 1. ? the terminal a1 corner must be identified on the t op surface by using a corner chamfer, ink or metallized markings, or other feature of package body or integral heat slug. ? a distinguishing feature is allowable on the bottom surface of the package to identify the terminal a1 corner. exact shape of eac h corner is optional.
ordering information STA8088EXG 22/24 docid022725 rev 6 4 ordering information figure 4. ordering information scheme packing gnss automotive grade sta8088ex tr ga example code: family identifier package option 8 tr = tape and reel = tray 8 = tfbga169 (12 x 12 x 1.2 mm) = tfbga169 (9 x 9 x1.2 mm) a = st automotive grade (with can) = aec-q100 (no can) g = gps/glonass/galileo/qzss = gps/qzss soc family
docid022725 rev 6 23/24 STA8088EXG revision history 23 5 revision history table 13. document revision history date revision changes 23-jan-2012 1 initial release. 26-mar-2012 2 updated features list table 4: main function pins : ? usb_dp/uart1_tx, usb_dm/uart1_rx: updated i/o added section 3.3: tfbga169 12 x 12 x 1.2 mm package information updated figure 4: ordering information scheme 14-dec-2012 3 changed document title from ?flexible gps/galileo/glonass/qzss receiver with high performance processing (arm9)? to ?flexible gps/galileo/glonass/compass/qzss receiver with high performance processing (arm9)? features , description , chapter 1: overview and figure 4: ordering information scheme : added compass constellation 16-sept-2013 4 updated disclaimer 07-jan-2014 5 removed compass features. 24-sep-2014 6 table 4: main function pins : ? rstn, wakeup: added note table 5: test/emulated dedicated pins : ? trstn: added note
STA8088EXG 24/24 docid022725 rev 6 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved

▲Up To Search▲

Price & Availability of STA8088EXG

	To Download STA8088EXG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .